The present invention relates to a technique for manufacturing a semiconductor integrated circuit, particularly a technique effective when applied to the fabrication of a semiconductor integrated circuit device having a step of depositing a silicon nitride film over a substrate by using thermal CVD (Chemical Vapor Deposition).
In a manufacturing process of a highly miniaturized and highly integrated LSI which has been adopted in recent days, a shallow groove isolation (SGI) is formed in a silicon substrate or a contact hole is formed in self alignment with a gate electrode of MISFET (Metal Insulator Semiconductor Field Effect Transistor) by making use of a difference in an etching rate between a silicon oxide film and a silicon nitride film. A formation process of such a shallow groove isolation (SGI) is described, for example, in Japanese Patent Application Laid-Open No. Hei 11(1999)-16999, while a formation process of such a self align contact (SAC) is described, for example, in Japanese Patent Application Laid-Open No. Hei 11(1999)-17147.
It is the common practice to form a silicon nitride film, which is utilized in the forming step of the above-described shallow groove isolation or self align contact, by thermal CVD using monosilane (SiH4) and ammonia (NH3) as a source gas. As a CVD reactor, employed is a batch-system hot-wall thermal CVD reactor for heat treating a plurality of semiconductor wafers (ex. 100 wafers or so) simultaneously. This hot-wall thermal CVD reactor adopts an indirect heating system of semiconductor wafers (radiation heating of semiconductor wafers by a heater outside a pipe wall) and it has a structure such that the inside wall of a chamber (reaction chamber) and the whole atmosphere in the chamber are heated to a temperature not less than the decomposition temperature of the source gas. In addition, since the source gas must be diffused in a large-volume chamber of this batch-system thermal CVD reactor, this reactor adopts low pressure CVD wherein a film is usually formed under reduced pressure conditions not greater than 0.13 kPa (1 Torr).
The present inventors have investigated on the film forming technique of a silicon nitride film by thermal CVD. The following is the outline of it.
The batch-system hot-wall thermal CVD reactor widely used for the formation of a silicon nitride film is structured to heat the whole atmosphere in the chamber (reaction chamber) so that a reaction product is deposited even on the inside wall of the chamber and becomes a cause for contamination of a wafer. In addition, cumbersome washing must be conducted frequently for removing this deposit from the inside wall of the chamber.
As described above, in the batch-system thermal CVD reactor, film formation is conducted under reduced pressure conditions not greater than 0.13 kPa (1 Torr), which retards a film forming rate. To make up for this retardation, about 100 wafers are treated simultaneously. With a rise in the volume of the chamber accompanied by an increase in the diameter of a wafer, it takes much time to diffuse a source gas uniformly, leading to a deterioration in the through-put of film formation. In a batch-system reactor for simultaneously treating a larger number of wafers, there also occur problems such as difficulty in maintaining a uniform film thickness within the face of the wafer and dislocation of wafer.
Recently, there is a tendency to adopt, as a countermeasure against a reduction in the threshold voltage of the miniaturized MISFET, a so-called dual gate CMOS structure (or also called CMIS (Complementary Metal Insulator Semiconductor)) wherein the gate electrode of an n channel type MISFET is made of n-type polycrystalline silicon and the gate electrode of a p channel type MISFET is made of p-type polycrystalline silicone and both serve as a surface channel type.
In this case, there is a potential danger that by the high temperature heat treatment after formation of a gate electrode, p-type impurity (boron) in the gate electrode made of p-type polycrystalline silicon may be diffused in a semiconductor substrate (well) through a gate oxide film, thereby causing fluctuations in the threshold voltage of MISFET. Deposition of a silicon nitride film after formation of the gate electrode therefore needs precise control of temperature conditions upon film formation. It is however difficult to set temperature conditions precisely in the above-described batch system thermal CVD reactor.
Plasma CVD is known as a method capable of depositing a silicon nitride film at a relatively low temperature without causing fluctuations of the characteristics of MISFET. It however involves drawbacks such as damage of a gate oxide film by plasma and charging up. It is therefore difficult to apply this method to formation of a silicon nitride film for sidewall spacers or silicon nitride film for self align contact.
In a single-wafer thermal CVD reactor which treats wafers one by one in one chamber, on the other hand, the volume of the chamber can be lowered compared with the above-described batch system thermal CVD reactor, which makes it possible to control temperature conditions precisely and improve the uniformity of the film thickness of a large-diameter wafer within its face. In addition, a source gas can be diffused uniformly and promptly even under sub-atmospheric reduced pressure conditions of 1.3 kPa (10 Torr) to 93 kPa (700 Torr), higher than the pressure conditions of the batch-system thermal CVD reactor, which makes it possible to improve a film forming velocity. In addition, by treating wafers one by one, the flow of wafer treatment is not interrupted so that a cycle time of a wafer process can be shortened and work in process can be reduced.
In order to make up for a reduction in the through-put due to treatment of wafers one by one, this single-wafer thermal CVD reactor adopts a cold wall system of heating only the wafer and its vicinity, so that there is not a potential danger of wafers being contaminated with reaction products deposited on the inside wall of the chamber and washing of the inside wall of the chamber is lightened.
Based on these investigation results, the present inventors reach a conclusion that use of a single-wafer cold-wall thermal CVD reactor is effective for the formation of a silicon nitride film required to have highly uniform thickness, for example, a silicon nitride film for side wall spacers or self align contact on a wafer having a diameter as large as about 20 to 30 cm.
The present inventors however found a new problem while investigating the introduction of a single-wafer cold-wall thermal CVD for the manufacturing process of a memory LSI under development.
In general, a memory LSI includes, in one chip, a memory mat and a peripheral circuit. In the memory mat, MISFETs constituting a memory cell are disposed with a markedly high density in order to realize a large-scale memory capacity, while in the peripheral circuit, MISFETs are disposed not so densely. On each of a plurality of chip regions sectioned on a wafer, there appears a region wherein gate electrode patterns are formed with low density (peripheral circuit) and a region with high density (memory mat).
When a silicon nitride film was deposited over such a wafer by thermal CVD, there appeared a phenomenon that in each of the plurality of chip regions, the silicon nitride film over the memory mat is thinner by about 30% than that over the peripheral circuit. This is presumed to occur because the effective surface area per wafer unit area is larger in the high-density region of gate electrodes (memory mat) than in the low-density region (peripheral circuit), which causes, in the former region, a relative shortage in the feed amount of a source gas and in turn, decreases a film deposition amount.
When such a problem (uneven film thickness) occurs, upon formation of side wall spacers on the side walls of the gate electrode of a memory mat or on the side walls of a peripheral circuit or formation of a contact hole in self alignment with the gate electrode or shallow groove isolation by dry etching of a silicon nitride film, complete etching of the thick silicon nitride film deposited over the peripheral circuit removes not only a thin silicon nitride film deposited over the memory mat but also the surface of the underlying film (gate oxide film or substrate), resulting in deterioration in the characteristics of MISFETs constituting a memory cell.
It is generally considered that the film forming mechanism of a silicon nitride film by thermal CVD using monosilane (SiH4) and ammonia (NH3) as a source gas owes to endothermic reaction by which silicon nitride (Si3N4) is formed as a result of thermal decomposition of monosilane (SiH4) and ammonia (NH3) as shown in the following equation (1):
3SiH4+4NH3xe2x86x92Si3N4+12H2xe2x80x83xe2x80x83(1)
In this reaction, the formation rate of silicon nitride is determined by the feed amount of monosilane (SiH4).
When a silicon nitride film is deposited over a wafer having both a high pattern density region and a low pattern density region, a difference in the thickness of the silicon nitride film between the memory mat and peripheral circuit can be reduced by increasing a flow rate ratio (SiH4/NH3) of monosilane to ammonia, thereby supplying a sufficient amount of monosilane to the memory mat having a larger effective surface area.
Upon deposition of a silicon nitride film over a wafer by using a single-wafer cold-wall thermal CVD reactor, the present inventors increased a flow rate ratio of monosilane based on the above-described presumption. Contrary to their expectation, a difference in film thickness between the memory mat and peripheral circuit was not decreased. The present inventors therefore searched for its cause and drew a conclusion as described below.
When a hot-wall batch-system CVD reactor which heats the whole atmosphere in the chamber, a source gas introduced into the chamber is heated to a temperature not less than the decomposition point of monosilane and ammonia before it reaches the surface of the wafer. A thermally decomposed gas is therefore fed to the surface of the wafer. In a single-wafer cold-wall thermal CVD reactor which heats only a stage (susceptor) to have a wafer mounted thereon, on the other hand, the temperature of only the wafer and its vicinity becomes high so that monosilane and ammonia in the source gas are thermally decomposed not rightly after they are introduced into the chamber but after they reach the vicinity of the surface of the wafer. The decomposition rate of ammonia having a decomposition temperature higher by about 250xc2x0 C. than monosilane becomes relatively slow compared with monosilane, resulting in shortage in the amount of nitrogen atoms supplied to the surface of the wafer. In this case, even by an increase in the feed amount of monosilane, film formation rate of a silicon nitride film over a memory mat cannot be improved.
The present inventors thus revealed that it is impossible to apply, to film formation of a silicon nitride film by using a single-wafer cold-wall thermal CVD reactor, a forming mechanism of the silicon nitride film that when a conventional hot-wall batch-system CVD reactor is used, an uneven film appears because a film formation rate is determined depending on the feed amount of monosilane (SiH4).
An object of the present invention is to provide a technique capable of reducing, upon deposition of a silicon nitride film by thermal CVD over a semiconductor wafer having a low pattern density region and a high pattern density region, a difference in the thickness of the silicon nitride film between the low pattern density region and high pattern density region.
The above-described object, the other objects and novel features of the present invention will be apparent from the description herein and accompanying drawings.
Of the inventions disclosed in this application, typical ones will next be summarized.
In one aspect of the present invention, there is thus provided a manufacturing method of a semiconductor integrated circuit device which comprises (a) depositing a first silicon nitride film over the main surface of a semiconductor substrate by thermal CVD using a first source gas containing a silane-based gas and an ammonia gas; (b) forming, over the main surface of the semiconductor substrate, a plurality of first patterns having a low pattern density region and a high pattern density region; and (c) depositing a second silicon nitride film over the main surface of the semiconductor substrate, which has a plurality of first patterns formed thereover, by thermal CVD using a second source gas containing a silane-based gas and an ammonia gas; wherein the first source gas and second source gas are different from each other in a flow rate ratio of said silane-based gas to said ammonia gas.
In another aspect of the present invention, there is also provided a manufacturing method of a semiconductor integrated circuit device, which comprises (a) depositing a first silicon nitride film over the main surface of a semiconductor wafer by thermal CVD using a first source gas containing a silane-based gas and an ammonia gas; (b) forming, over the main surface of the semiconductor wafer, a plurality of first patterns having a low pattern density region and a high pattern density region; and (c) depositing a second silicon nitride film over the main surface of the semiconductor substrate, which has a plurality of first patterns formed thereover, by thermal CVD using a second source gas containing a silane-based gas and an ammonia gas; wherein the second source gas is larger than the first source gas in a flow rate ratio of the ammonia gas to the silane-based gas.
In a further aspect of the present invention, there is also provided a manufacturing method of a semiconductor integrated circuit device, which comprises (a) depositing a first silicon nitride film over the main surface of a semiconductor wafer by thermal CVD using a first source gas containing a silane-based gas and an ammonia gas; (b) forming, over the main surface of the semiconductor wafer, a plurality of gate electrodes having a low pattern density region and a high pattern density region; (c) depositing a second silicon nitride film over the main surface of the semiconductor wafer, which has said plurality of gate electrodes formed thereof, by thermal CVD using a second source gas containing a silane-based gas and an ammonia gas; and (d) forming side wall spacers made of the second silicon nitride film on side walls of each of the plurality of gate electrodes by anisotropic etching of the second silicon nitride film; wherein the second source gas is larger than the first source gas in a flow rate ratio of the ammonia gas to the silane gas.
It should be noted that in the present application, the term xe2x80x9csemiconductor integrated circuit devicexe2x80x9d means not only that formed over a single crystal silicon substrate but also that formed on another substrate such as SOI (Silicon On Insulator) substrate or a substrate for fabricating TFT (Thin Film Transistor) liquid crystals unless otherwise specifically indicated. The term xe2x80x9cwaferxe2x80x9d as used herein means a single silicon substrate (usually, an almost disk shape), SOI substrate, glass substrate and the other insulating, semi-insulating or semiconductor substrate, and composite thereof, each used for the fabrication of a semiconductor integrated circuit device.
The term xe2x80x9cchipxe2x80x9d or xe2x80x9cchip regionxe2x80x9d means a unit of an integrated circuit region as illustrated in FIG. 1 corresponding to a portion of a wafer sectioned after all the steps are completed.
The term xe2x80x9csub-atmospheric reduced pressure regionxe2x80x9d usually means a pressure range of 1.3 kPa to 93 kPa. The term xe2x80x9csub-atmospheric pressurized regionxe2x80x9d means, in this application, a pressure range of 106 kPa to 133 kPa and a region including this region and an atmospheric pressure region is called xe2x80x9csub-atmospheric pressure regionxe2x80x9d.
A single-wafer cold-wall thermal CVD reactor is usually a CVD reactor which is a cold wall type heat treating furnace permitting heating (resistance heating, high frequency induction heating or lamp heating) of a wafer to a temperature higher than the peripheral wall of the reactor and film formation wafer by wafer without directly heating using, for example, plasma.
A gas atmosphere may contain, in addition to a reactant gas, carrier gas and dilution gas, an additive gas. When a reference is made to a gas composition, the gas composition is permitted to contain another component unless otherwise specifically indicated.
In the below-described embodiments, reference is made to the number (including the number, numerical value, quantity and range) of elements. The number of the elements is however not limited to a specific one and elements may be used in the number less or greater than the specific number unless otherwise particularly indicated or apparently limited to a specific number in principle. Furthermore in the below-described embodiments, it is obvious that constituting elements (including elemental steps or the like) are not always indispensable unless otherwise particularly specified or unless otherwise presumed to be apparently indispensable in principle.
Similarly, when reference is made to the shape, positional relationship or the like of constituting elements, those substantially close or similar to their shapes or the like are included unless otherwise specifically indicated or presumed to be apparently different in principle. This also applies to the above-described numerical value and range.